1. Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a silicon oxide and silicon glass deposition using a combined power-optimized Plasma-Activated CVD with tetraethoxysilane-ozone-oxygen reaction gas mixture (TEOS-O.sub.3 /O.sub.2 PACVD).
2. Description of the Prior Art
In the fabrication of devices such as semiconductor devices, a variety of material layers is sequentially formed and processed on the substrate. (For the purpose of this disclosure, the substrate includes a bulk material such as semiconductor, e.g., silicon, body, and if present, various regions of materials such as dielectric materials, conducting materials, metallic materials, and/or semiconductor materials). Often, one of the material regions utilized in this fabrication procedure includes a silicon oxide, i.e., a material nominally represented by the formula SiO.sub.n, where n=.about.2. For example, silicon oxide regions are utilized as insulating/passivating layers as electrical insulation between conducting layers, e.g., polysilicon or metal layers, and as a cap doped semiconductor layers to limit unacceptable dopant migration during subsequent processing.
A silicon oxide is often deposited on a non-planar substrate having a plurality of steps, e.g., conducting steps. Substrate represents a semiconductor structure 10 and overlying layers (e.g., lines 112). It is desirable that the deposited silicon oxide conformally coats this non-planar surface. If a conformal silicon oxide layer is not achieved, an irregular coating, (118 in FIG. 1), forms over the underlying steps, 112. If deposition is continued, voids, 110, as shown in FIG. 2, are often produced. An irregular coating such as shown in FIG. 1 is, in many situations, unacceptable because a non-planar surface degrades the resolution of subsequent photolithography. Voids such as shown in FIG. 2 are even less desirable because etching and dielectric properties will be non-uniform. In either case, lack of planarity generally produces difficulties in subsequent processing. Therefore, it is very desirable to produce a conformal coating.
The prior art processes do not provide conformal oxide layer that can conformally cover on and between the increasingly tight step features of new semiconductor devices without forming seams.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following:
U.S. Pat. No. 5,593,741 (Ikeda) Method and apparatus for forming silicon oxide film by chemical vapor deposition--shows oxide and oxynitride film Plasma-Enhanced Chemical Vapor Deposition methods in parallel plate reactor type (PECVD), or electron cyclotron resonance type (ECR) reactor with about 1 second cycled-plasma excitation of the gas mixture to provide cycled concentration of the high degree ionized molecules.
U.S. Pat. No. 5,271,972 (Kwok) Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity--teaches a method of depositing good quality thermal CVD silicon oxide layers over a PECVD TEOS/oxygen silicon oxide layer comprising forming an interstitial layer by ramping down the power in the last few seconds of the PECVD deposition. This invention has a step with the lowering of the plasma power of PECVD film deposition that helps to reduce the surface sensitivities of the following TEOS-ozone SACVD oxide.
U.S. Pat. No. 5,643,839 (Dean) Low temperature deposition of silicon oxides for device fabrication--teaches a deposition process involving a plasma struck in a gas including tetraethoxysilane and source of oxygen yields, at low temperatures, conformal coatings of silicon dioxide.
U.S. Pat. No. 5,362,526 (Wang) Plasma-Enhanced CVD process using TEOS for depositing silicon dioxide--teaches a multi-step deposition process. The CVD SiO2 process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer is described. Various combinations of the steps are disclosed for different applications.